Coaxial via in PCB for high-speed signaling designs

ABSTRACT

A method of fabricating a printed circuit board having a coaxial via is disclosed. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.

FIELD

The present invention relates broadly to PCB assembly, and, morespecifically, to configuring a coaxial via through stacked layers of aPCB.

BACKGROUND OF THE INVENTION

Printed circuit boards (PCBs) are typically constructed from two or morelayers sandwiched together but separated by dielectric material. Layerscan have different thicknesses and different dielectric material can beused within a PCB. Routing or other kinds of copper structures can beimplemented at all layers. The outermost layers (top and bottom) of thePCB can have components mounted on their outside surfaces. MultilayerPCBs provide an important advantage over single layer structures in thata multilayer PCB has more routing space in a smaller footprint, which isuseful for today's design imperative of smaller-size components.

Vias interconnect traces on different PCB layers and connect layers topower and/or ground planes. The physical properties of a via aredictated by board geometry and available space, and also by application.For example, in high-speed signaling applications, impedance-matchedtransitions are required between layers, particularly as frequencies inthe Gigahertz range are utilized on the PCB.

In high-speed signaling designs, impedance continuity is essential forall of the interconnect elements including traces, connectors, cablesand the like. Among all of these interconnect elements, the via presentsthe greatest obstacle to achieving impedance control, becausetraditional PCB process flow does not allow fabrication of coxial vias.Coaxial via technology is greatly needed for high-frequency applicationsas it would enable true signal impedance continuity, provide anexcellent return path for ground (GND), and efficiently reducevia-to-via crosstalk and via-to-trace crosstalk.

One prior approach has been to surround a signal via with multiple GNDvias. With this approach, the return path and impedance control aregreatly improved. However, the additional GND vias consume valuablespace on the footprint of a multilayer PCB. To save space, another priorapproach was to split the via into four pieces so that one pair servesas signal vias and the other pair serve as GND vias. Unfortunately,performance of this dissected-via approach is unacceptable. Thus, thereremains a heartfelt need for improved impedance control and performancein vias configured in multilayer PCBs.

SUMMARY OF THE INVENTION

The present invention solves the problems described above by presentinga coaxial via in a multilayer PCB. In the present invention, the platedwall of the via serves as the ground return of the coaxial via. It alsoconnects all of the ground layers within the PCB. In one aspect, thepresent invention provides a method of fabricating a printed circuitboard (PCB) having a coaxial via. First assembled is a stack of layershaving a top signal layer and a bottom signal layer. A hollow via isformed through the stack to connect all of the GND layers, and aconductor coated with non-conductive material is inserted in the via.The top layer and bottom layer are first covered with dielectric andpatterned signal layers, and then with a masking agent. In anembodiment, the masking agent is photoresist. The top layer and bottomlayer are then plated with conductive material to connect signal traceswithin the via, and the masking agent is removed from the top layer andbottom layer. In an embodiment, multiple printed circuit board layerscan be fabricated using this method and then laminated together in astacked configuration, with each printed circuit board layer in thestacked configuration having its via disposed such that it aligns with avia on a neighboring printed circuit board in the stacked configuration.

In another aspect, the present invention provides a method offabricating a printed circuit board having a via, comprising assemblinga plurality of layers configured in a stack so that the plurality oflayers has a top layer and a bottom layer. A hollow via is formedthrough the plurality of layers and filled with dielectric material. Ahole is formed through the dielectric material to form an aperture thatconnects the top layer and the bottom layer. Provided within theaperture, either by insertion or by forming it in place, is a conductorcoated with non-conductive material. The top signal layer 23 and bottomsignal layer 25 are covered with dielectric and patterned signal layers,then covered with a masking agent. The top layer and bottom layer arethen plated with a conductive material that connects signal traceswithin via and the masking agent is removed from the top layer andbottom layer. In an embodiment, multiple printed circuit board layerscan be fabricated using this method and then laminated together in astacked configuration, with each printed circuit board layer in thestacked configuration having its via disposed in it such that it alignswith a via on a neighboring printed circuit board in the stackedconfiguration.

Other features and advantages of the present invention will be apparentfrom the following detailed description, when considered in conjunctionwith the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a multi-layer PCB having an aperture formed thereinthat accommodates a coaxial via.

FIG. 2 illustrates the multi-layer PCB of FIG. 1 covered with dielectricand patterned signal layers.

FIG. 4 illustrates the multi-layer PCB partially covered with a maskingagent to define the dielectric layer to expose signal segments forplating.

FIG. 5 illustrates the multi-layer PCB with of FIG. 4 with the maskingagent removed.

FIG. 6 illustrates the multi-layer PCB with masking layers applied totop and bottom surfaces for plating.

FIG. 7 illustrates the multi-layer PCB with plating layers applied totop and bottom surfaces.

FIG. 8 illustrates the multi-layer PCB with masking layers removed.

FIG. 9 illustrates a multi-layer PCB having a via filled with dielectricmaterial.

FIG. 10 illustrates the multi-layer PCB of FIG. 9 with an apertureformed within the via filled with dielectric material.

FIG. 11 illustrates the multi-layer PCB of FIG. 13 with a coaxial viainserted within the aperture formed in the dielectric material.

FIG. 12 illustrates a plurality of multi-layer PCBs before they areassembled together in a stack.

FIG. 13 illustrates the multi-layer PCBs of FIG. 12 after they areassembled together in a stack.

DETAILED DESCRIPTION

FIGS. 1-13 illustrate cutaway views of multi-layer PCBs in variousstages of completion in accordance with embodiments of the presentinvention. Dimensions of the PCB illustrated in FIGS. 1-13 in some caseshave been exaggerated for clarity. Directing attention to FIG. 1, thereis shown PCB 10, having a plurality of layers 12 arranged in a stack andhaving formed thereon an aperture that provides via 14. As illustrated,PCB 10 includes dielectric layers 22 and ground layers 24, but powerlayers can also be substituted for at least some of ground layers 24 inalternative embodiments. In an embodiment, via 14 has applied to itssurface within the aperture a conductive coating material 15. Conductivecoating material 15 serves as the ground return of the coaxial via. Italso connects all of the GND layers 24 within PCB 10. Coaxial via 16 isinserted within via 14. Coaxial via 16 is illustrated with conductivemember 18 surrounded by insulating layer 20. In FIG. 2, signal layers23, 25 are added, and in FIG. 3 additional dielectric layers 22 aresubsequently added. As shown in FIG. 4, masking material, such asphotoresist, is applied to form masking layers 26 that define underlyingdielectric layer 22 to expose signal segments for plating. Maskinglayers 26 are then removed, as shown in FIG. 5. In the preferredembodiment, photoresist is removed through known processes.

Directing attention to FIG. 6, masking layers 26 are again applied toPCB 10's top and bottom surfaces. In FIG. 7, plating layers 28, 29 areadded. After plating layers 28, 29 are added, the masking layers 26 areremoved, and PCB 10 has plating layers 28, 29 connected by coaxial via16.

In another embodiment, the present invention provides a via filled withdielectric material formed within PCB. An aperture is formed within thedielectric material and a coaxial via is inserted in the aperture.Directing attention to FIG. 9, multi-layer PCB 50 is constructed fromdielectric layers 62 and GND layers 64, and includes via 52 havingapplied to its surface conductive coating material 53. Via 52 is thenfilled with dielectric material 54. Aperture 56 is then formed throughdielectric material 54, as shown in FIG. 10. Plating aperture 56 withconductive material 60 completes coaxial via 58, having conductivemember 60, dielectric layer 54 and shield layer 53, as shown in FIG. 11.PCB 50 is then processed as described above with reference to FIGS. 2-5.First, dielectric layers are applied to the top and bottom surfaces ofPCB 50. Signal layers are applied after the dielectric layers areapplied. PCB 50 is then prepared for plating, by adding masking materialto the top and bottom surfaces of PCB 50. PCB 50 is then plated on bothtop and bottom surfaces, and the masking material is removed. In thepreferred embodiment, the masking material is photoresist, and itsremoval is performed using known methods.

Photoresist may be applied using a variety of techniques includingdipping PCB 10, 50 in photoresist solution, or spraying, brushing orrollercoating the solution on the desired surface. Following theapplication of photoresist, excess solvents can be baked out of PCB 10,50 using known techniques, such as subjecting PCB 10, 50 to acirculating current of hot air or heat produced by an infrared light orother radiating heat source focused on PCB 10, 50.

During the plating process contemplated by embodiments of the presentinvention, metal is applied to provide effective connection between thetop surface and the bottom surface of PCB 10, 50, by completing aconnection through the formed via and across coaxial via 16. The chosenmetal should have a high electrical conductivity so high current iseasily carried without voltage drops. There also should be goodadherence of the chosen metal to the underlying surfaces of layerssurrounding via 16.

Directing attention to FIGS. 12 and 13, embodiments of the presentinvention assemble multiple PCBs 10, 50 into a single, multi-layer PCB100 through sequential lamination of PCB layers 80, 82, 84. In thismanner, via 86 connects at least one interior layer 88 with anotherlayer 90 in a multi-layer PCB, as is useful for half-blind vias. Whilethe dimensions of PCB layers 80, 82, 84 are exaggerated in FIGS. 12 and13 for clarity, it is to be understood that actual thicknesses of metallayers do not interfere with lamination of PCB layers 80, 82, 84 in FIG.12 into multi-layer PCB 100. It is also to be understood that, whilethree PCB layers are illustrated in FIG. 12, additional PCB layers canbe included in the construction of multi-layer PCB 100. Variousadhesives as are used in the lamination of existing PCB boards can beused in the lamination of PCB layers 80, 82, 84. Furthermore, while PCBlayers 80, 82, 84 all contain ground and/or power layers, In anembodiment, some layers that do not have power or ground layers but havethe coaxial via of the present invention can be included in the finalassembly.

PCBs 10, 50, 100 may contain etched conductors attached to a sheet ofinsulator. The conductive etched conductors are also referred to astraces or tracks. The insulator is referred to as the substrate. Inaccordance with various embodiments of the present invention, PCB 10, 50can be constructed using a variety of methods. Construction of PCBs 10,50, 100 can incorporate etch-resistant inks to protect the copper foilon the outer surfaces or component surfaces of multi-component stackedembodiments of the present invention. Subsequent etching removesunwanted copper. Alternatively, the ink may be conductive, printed on ablank (non-conductive) board in embodiments involving hybrid circuitapplications. Construction of PCBs 10, 50, 100 can also incorporate aphotomask and chemical etching to remove the copper foil from thesubstrate, as described above. PCBs 10, 50, 100 can also be constructedusing a 2- or 3-axis mechanical milling system to mill away the copperfoil from the substrate.

In accordance with embodiments of the present invention, PCBs 10, 50,100 can incorporate substrates made from paper impregnated with phenolicresin, sometimes branded Pertinax™. In other embodiments, substrates areconstructed from a material designated FR-4. In yet other embodiments,substrates are constructed from plastics with low dielectric constant(permittivity) and dissipation factor, such as Rogers® 4000, Rogers®Duroid, DuPont® Teflon® (types GT and GX) brand products, polyimide,polystyrene and cross-linked polystyrene. For applications where aflexible PCB is useful, PCBs 10, 50, 100 can incorporate substratesconstructed from DuPont's® Kapton® brand polyimide film, and others.

PCBs 10, 50, 100 can also incorporate a conformal coat that is appliedby dipping or spraying after components on PCB 10, 50 have beensoldered. The conformal coats be dilute solutions of silicone rubber orepoxy, or plastics sputtered onto PCBs 10, 50, 100 in a vacuum chamber.

While the preferred embodiments of the present invention have beenillustrated and described in detail, it is to be understood thatnumerous modifications can be made to embodiments of the presentinvention without departing from the spirit thereof.

1. A method of fabricating a printed circuit board having a via, themethod comprising: assembling a plurality of layers configured in astack so that the plurality of layers has a top layer and a bottom layerand at least one conductive layer within the stack; forming a hollow viathrough the plurality of layers, the hollow via having an interiorsurface defining a space; applying a conductive material to the interiorsurface, the conductive material connecting to the at least oneconductive layer within the stack; within the hollow via, providing aconductor coated with non-conductive material; covering the top layerand bottom layer with dielectric layers; covering the top layer andbottom layer with a masking agent; plating the top layer and bottomlayer with a conductive material that connects to the conductor coatedwith nonconductive material; and removing the masking agent from the toplayer and bottom layer.
 2. The method of claim 1, wherein the at leastone conductive layer comprises a at least one ground layer.
 3. Themethod of claim 1, wherein the at least one conductive layer comprisesat least one power layer.
 4. The method of claim 1, wherein providingthe conductor comprises inserting the conductor coated withnonconductive material.
 5. The method of claim 1, wherein providing theconductor comprises forming within the hollow via the conductor coatedwith nonconductive material.
 6. The method of claim 1, wherein forming ahollow via comprises filling a hollow via with dielectric material anddrilling a hole through the dielectric material.
 7. A method offabricating a printed circuit board having a via, the method comprising:assembling a plurality of layers configured in a stack so that theplurality of layers has a top layer and a bottom layer and at least oneconductive layer within the stack; forming a hollow via through theplurality of layers, the hollow via having a surface that defines aspace; applying a conductive material to the surface, the conductivematerial connecting to the at least one conductive layer; filling thehollow via with dielectric material; drilling a hole through thedielectric material to form an aperture that connects the top layer andthe bottom layer; providing within the aperture via a conductor coatedwith non-conductive material; covering the top layer and bottom layerwith dielectric layers; covering the top layer and bottom layer with amasking agent; plating the top layer and bottom layer with a conductivematerial that connects to the conductor; and removing the masking agentfrom the top layer and bottom layer.
 8. The method of claim 7, whereinthe at least one conductive layer comprises at least one ground layer.9. The method of claim 7, wherein the at least one conductive layercomprises at least one power layer.
 10. The method of claim 7, whereinproviding the conductor comprises inserting the conductor coated withnonconductive material.
 11. The method of claim 7, wherein providing theconductor comprises forming within the hollow via the conductor coatedwith nonconductive material.
 12. A method of fabricating a printedcircuit board, comprising: fabricating a plurality of printed circuitboard layers, wherein each layer fabricated by: assembling a pluralityof layers configured in a stack so that the plurality of layers has atop layer and a bottom layer and at least one conductive layer; forminga hollow via through the plurality of layers, the hollow via having asurface that defines a space; applying a conductive material to thesurface; within the hollow via, providing a conductor coated withnon-conductive material; covering the top layer and bottom layer withdielectric layers; covering the top layer and bottom layer with amasking agent; plating the top layer and bottom layer with a conductivematerial that connects signal traces within via; and removing themasking agent from the top layer and bottom layer; and laminatingtogether in a stacked configuration the plurality of printed circuitboard layers.
 13. The method of claim 12, wherein the at least oneconductive layer comprises at least one ground layer.
 14. The method ofclaim 12, wherein the at least one conductive layer comprises at leastone power layer.
 15. The method of claim 12, wherein providing theconductor comprises inserting the conductor coated with nonconductivematerial.
 16. The method of claim 12, wherein providing the conductorcomprises forming within the hollow via the conductor coated withnonconductive material.
 17. A method of fabricating a printed circuitboard, comprising: fabricating a plurality of printed circuit boardlayers, wherein each layer fabricated by: assembling a plurality oflayers configured in a stack so that the plurality of layers has a toplayer and a bottom layer and at least one conducting layer; forming ahollow via through the plurality of layers; applying a conductivematerial to a surface defining the hollow via, the conductive materialin contact with the at least one conductive layer; filling the hollowvia with dielectric material; drilling a hole through the dielectricmaterial to form an aperture that connects the top layer and the bottomlayer; providing within the aperture via a conductor coated withnon-conductive material; covering the top layer and bottom layer withdielectric layers; covering the top layer and bottom layer with amasking agent; plating the top layer and bottom layer with a conductivematerial that connects to the conductor located within the via; andremoving the masking agent from the top layer and bottom layer: andlaminating together in a stacked configuration the plurality of printedcircuit board layers.
 18. The method of claim 17, wherein the at leastone conductive layer comprises at least one ground layer.
 19. The methodof claim 17, wherein the at least one conductive layer comprises atleast one power layer.
 20. The method of claim 17, wherein providing theconductor comprises inserting the conductor coated with nonconductivematerial.
 21. The method of claim 20, wherein providing the conductorcomprises forming within the hollow via the conductor coated withnonconductive material.
 22. A printed circuit board, comprising: aplurality of layers configured in a stack so that the plurality oflayers has a top layer and a bottom layer and at least one conductivelayer; a hollow via through the plurality of layers; within the hollowvia, a conductive material applied to a surface defining the hollow via,and a conductor coated with non-conductive material; wherein the toplayer and bottom layer are covered by dielectric layers and the toplayer and bottom layer with are plated with a conductive material thatconnects to the conductor within via.
 23. The printed circuit board ofclaim 22, wherein the at least one conductive layer comprises at leastone ground layer.
 24. The printed circuit board of claim 22, wherein theat least one conductive layer comprises at least one power layer.
 25. Aprinted circuit board, comprising: a plurality of printed circuit boardlayers laminated together in a stacked configuration to form a singleprinted circuit board, wherein each printed circuit board layer inlaminated stacked configuration comprises a plurality of layersconfigured in a stack so that the plurality of layers has a top layerand a bottom layer and at least one conductive layer; a hollow viaformed through the plurality of layers, the hollow via having a definingsurface, the defining surface having a conductive material appliedthereon, the conductive material connecting to the at least one groundlayer; within the hollow via, a conductor coated with non-conductivematerial; wherein the top layer and bottom layer are covered bydielectric layers and the top layer and bottom layer with are platedwith a conductive material that connects to the conductor located withinvia; wherein a via in each printed circuit board is disposed within itsprinted circuit board layer such that it aligns with a via on aneighboring printed circuit board layer within the printed circuit boardlayers laminated together in the stacked configuration.
 26. The printedcircuit board of claim 25, wherein the at least one conductive layercomprises at least one ground layer.
 27. The printed circuit board ofclaim 25, wherein the at least one conductive layer comprises at leastone power layer.
 28. The printed circuit board of claim 25, wherein theconductor connects a signal layer on an outside surface of the stackedconfiguration with a conductive layer on an interior surface of thestacked configuration.
 29. A printed circuit board, comprising: aplurality of layers configured in a stack so that the plurality oflayers has a top layer and a bottom layer and at least one conductivelayer; a through via disposed through the plurality of layers, whereinthe via has applied to its inner surface a conductive material, theconductive material connecting to the at least one ground layer, whereinthe via is filled with dielectric material, the dielectric materialhaving an aperture that connects the top layer and the bottom layer; anda conductor coated with non-conductive material disposed within thedielectric material; wherein the top layer and bottom layer comprisedielectric layers and are plated with a conductive material thatconnects to the conductor located within via.
 30. The printed circuitboard of claim 29, wherein the at least one conductive layer comprisesat least one ground layer.
 31. The printed circuit board of claim 29,wherein the at least one conductive layer comprises at least one powerlayer.
 32. A printed circuit board, comprising a plurality of printedcircuit board layers laminated together in a stacked configuration toform a single printed circuit board, wherein each printed circuit boardlayer in the laminated stacked configuration comprises a plurality oflayers configured in a stack so that the plurality of layers has a toplayer and a bottom layer and at least one conductive layer and a throughvia disposed through the plurality of layers, wherein a conductivematerial is applied to a surface defining the through via, theconductive material applied to the surface connecting to the at leastone ground layer, wherein the via is filled with dielectric material,the dielectric material having an aperture that connects the top layerand the bottom layer; and a conductor coated with non-conductivematerial disposed within the dielectric material, wherein the top layerand bottom layer are covered by dielectric layers and the top layer andbottom layer with are plated with a conductive material that connects tothe conductor located within via; wherein the via in each printedcircuit board layer is disposed within its printed circuit board layersuch that it aligns with a via on a neighboring printed circuit boardlayer within the printed circuit board layers laminated together in thestacked configuration.
 33. The printed circuit board of claim 32,wherein the at least one conductive layer comprises at least one groundlayer.
 34. The printed circuit board of claim 32, wherein the at leastone conductive layer comprises at least one power layer.
 35. The printedcircuit board of claim 32, wherein the conductor connects a signal layeron an outside surface of the stacked configuration with a signal layeron an interior surface of the stacked configuration.